In a conventional, lithographically patterned device, a loss of charge due to leakage current may occur at cross-over locations where a gate electrode crosses over sharp/abrupt edges of an active feature (e.g., transistor channel) or other structure. FIG. 1 shows a conventional, lithographically defined transistor channel layer 102 formed over a substrate 101 and a dielectric layer 103 formed thereover. The dielectric layer 103, whether formed by oxidation or deposition, may have a non-uniform coverage of the lithographically formed channel layer 102 at the edges of the channel layer 102 (i.e., the upper edges of the channel layer 102 and where the channel layer 102 meets the substrate 101). A gate layer 104 is deposited over the dielectric 103. The dielectric layer may be substantially thinner at the edges of the channel layer 102, which can result in leakage current between the channel layer 102 and the gate layer 104 at the thinner parts of the dielectric layer 103.
Additionally, the gate layer 104 may cover the dielectric layer 103 and the channel 102 in a non-uniform manner. Blanket deposition of the gate layer 104 over a lithographically defined channel layer having sharp edges and substantially vertical sides may result in non-uniformity of the gate layer and discontinuities or gaps in the gate layer.
The leakage current and discontinuous gate layer deposition can be avoided by forming semiconductor features having smooth and/or dome-shaped geometry. Electrically active features having smooth and/or dome-shaped cross-sectional and/or longitudinal profiles can allow for smooth transitions without encountering sharp steps, preventing structural discontinuities during deposition of subsequent and/or overlying layers, and allowing for more complete step coverage of subsequently deposited structures. However, there have been challenges in precisely controlling certain critical dimensions in conventionally deposited or printed electrically functional features, especially high resolution dielectric, conductor, and semiconductor features.
Conventional printing processes may rely on an absorbing substrate (e.g., paper or cloth) to fix a position and a size of a deposited material (e.g., an ink). However, substrates typically used in manufacturing electronic devices are generally non-absorbing. The ink, as printed on a non-absorbing substrate, will behave as a liquid and will tend to move and/or spread until (or unless) the solvent is evaporated. Typically, the evaporation rate of the deposited ink is greatest near its edge, and liquid from the bulk of the deposited ink tends to flow to the edge as evaporation occurs, resulting in deposition of solute particles near the edge. This phenomenon is sometimes referred to as “coffee ring” formation. The coffee ring profile is undesirable for semiconductor, conductor and/or dielectric structures in microelectronic applications, and there is a need for printing processes that form semiconductor, conductor and dielectric features having a more uniformly distributed shape (e.g. a smooth, dome-shaped profile).